DocumentCode :
3478565
Title :
Experimental and simulation studies of single-electron-transistor-based multiple-valued logic
Author :
Inokawa, Hiroshi ; Takahashi, Yasuo
Author_Institution :
Basic Res. Labs., NTT Corp., Kanagawa, Japan
fYear :
2003
fDate :
16-19 May 2003
Firstpage :
259
Lastpage :
266
Abstract :
Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.
Keywords :
MOSFET; SPICE; multivalued logic; single electron transistors; CMOS-compatible pattern-dependent oxidation technology; PADOX; SET; SPICE circuit simulator; hybrid SET-MOSFET scheme; multiple-valued logic; performance estimation; periodic drain current-gate voltage characteristic; quantizer; single-electron transistor; universal literal gate; Logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2003. Proceedings. 33rd International Symposium on
ISSN :
0195-623X
Print_ISBN :
0-7695-1918-0
Type :
conf
DOI :
10.1109/ISMVL.2003.1201415
Filename :
1201415
Link To Document :
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