• DocumentCode
    347857
  • Title

    A comparative analysis of high-speed digital test techniques

  • Author

    Sachdev, Manoj ; Shashaani, Mansour

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
  • Volume
    1
  • fYear
    1999
  • fDate
    9-12 May 1999
  • Firstpage
    379
  • Abstract
    Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various implementation aspects of this technique are also addressed.
  • Keywords
    CMOS digital integrated circuits; VLSI; design for testability; integrated circuit testing; CMOS VLSI devices; DFT strategy; VLSI testers; design for test; high performance devices; high performance integrated circuits; high-speed digital test techniques; low performance testers; Circuit testing; Clocks; Costs; Frequency; Integrated circuit testing; Logic testing; Manufacturing; Ring oscillators; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1999 IEEE Canadian Conference on
  • Conference_Location
    Edmonton, Alberta, Canada
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-5579-2
  • Type

    conf

  • DOI
    10.1109/CCECE.1999.807228
  • Filename
    807228
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=347857