Optimization of a latched comparator for high-speed analog-to-digital converters

Reports on the optimization of a latched comparator for use in a high speed analog to digital converter (ADC). Optimization of the comparator was achieved through variations of transistor dimensions and layout designs. Specifically three layout styles, fill-analog style, partial-analog style and digital-like style were created in 0.5 /spl mu/m MOSIS and 0.35 /spl mu/m TSMC CMOS technologies. HSPICE simulation results show definite performance variations for comparators with different transistor dimensions and with different layout styles.