Fabrication of strained Si0.55Ge0.45 channel PMOSFETs directly on a Si substrate

Biaxial strained Si_0.55Ge_0.45 channel pMOSFETs were fabricated using a process compatible with traditional bulk Si CMOS devices. The thermal budget was carefully controlled in the device fabrication process to avoid strain relaxation. Channel materials were formed by pseudomorphic growth of 7nm strained Si_0.55Ge_0.45 directly on a Si substrate followed by a growth of a 4 nm Si cap. At room temperature, the strained Si_0.55Ge_0.45/Si p-MOSFETs showed a significant mobility enhancement of ~77% over Si control devices in a low vertical electric field. Moreover, the drain current of the long channel devices was increased by ~47% with a gate overdrive of 2.5V. It was also observed that the enhancement of effective hole mobility degraded as the vertical electric field increased.