A multi-megabit memory compiler: tomorrow´s IP [integrated processor]

Author

Zhang, Xian-Quan ; Tsang, Tony ; Mehta, Deepak

Author_Institution

Phys. Libr. Div., Mentor Graphics Corp., Warren, NJ, USA

Volume

1

fYear

1999

fDate

9-12 May 1999

Firstpage

538

Abstract

Millions of bits of memory are sometimes required in today´s system-on-a-chip designs. The scarcity of large ASIC memories forces designers to build their multi-megabit memories from smaller ones, with a concoction of design and analysis tools. This method can lead to many problems. We have developed a multi-megabit memory compiler that carries the full burden of the design assembly, verification and characterization for the ASIC designers. It saves valuable time and alleviates the risk for ASIC designers. In this paper, we describe the creation of the multi-megabit memory compiler with a set of commercially available EDA (electronic design automation) tools.

Keywords

application specific integrated circuits; circuit layout CAD; integrated memory circuits; memory architecture; microprocessor chips; ASIC memories; design assembly; electronic design automation tools; integrated circuit characterization; integrated circuit verification; integrated processor chip; microprocessor chips; multi-megabit memory compiler; system-on-a-chip designs; Application specific integrated circuits; Assembly; CMOS technology; Circuit analysis; Energy consumption; Graphics; Layout; Libraries; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1999 IEEE Canadian Conference on

Conference_Location

Edmonton, Alberta, Canada

ISSN

0840-7789

Print_ISBN

0-7803-5579-2

Type

conf

DOI

10.1109/CCECE.1999.807256

Filename

807256