A 6.25-Gbps 4-tap low-power decision feedback equalizer in 0.13µm CMOS technology

Author

Xuelin Zhang ; Yuan Wang ; Jian Cao ; Song Jia ; Ganggang Zhang ; Xing Zhang

Author_Institution

Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China

fYear

2013

fDate

3-5 June 2013

Firstpage

1

Lastpage

2

Abstract

A half-rate 4-tap decision feedback equalizer (DFE) is implemented in 0.13μm CMOS technology for low-power I/O links. Modified current-mode logic (CML) latches with PMOS loads are used in the new proposed DFE to achieve better power and area efficiency. The proposed DFE consumes only 1.914mW from a 1.2V supply when equalizing 6.25Gb/s data passing through a simulated low-pass channel with 18 dB of loss at 3.125 GHz, which is 39.5% lower than the traditional design with resistor loaded CML latches.

Keywords

CMOS logic circuits; current-mode logic; decision feedback equalisers; flip-flops; low-power electronics; CMOS technology; DFE; PMOS load; bit rate 6.25 Gbit/s; frequency 3.125 GHz; half-rate 4-tap low-power decision feedback equalizer; loss 18 dB; low-power I-O links; modified CML latches; modified current-mode logic latches; power 1.914 mW; resistor-loaded CML latches; simulated low-pass channel; size 0.13 mum; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Decision feedback equalizers; Latches; Solids; Decision feedback equalizer (DFE); I/O link; current-mode logic (CML) latch; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of

Conference_Location

Hong Kong

Type

conf

DOI

10.1109/EDSSC.2013.6628236

Filename

6628236