• DocumentCode
    347878
  • Title

    A fast signature simulation technique for PPSFP simulators

  • Author

    Khadour, Firas ; Sun, Xiaoling

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
  • Volume
    1
  • fYear
    1999
  • fDate
    9-12 May 1999
  • Firstpage
    543
  • Abstract
    This paper introduces a novel technique to speed up the simulation of multiple-input shift-register (MISR) signature computation. We explore the linear property of MISRs, which permits the use of a small look-up table to compute the signatures of MISR inputs independently. Two algorithms are proposed for modifying these signatures and combining them into a find signature. Experimental results show that the proposed signature compaction technique is faster than previous methods with very little extra memory required. The new scheme is designed to work in conjunction with the PPSFP fault simulators.
  • Keywords
    VLSI; circuit simulation; fault simulation; table lookup; PPSFP simulators; algorithms; fast signature simulation technique; find signature; linear property; multiple-input shift-register signature computation; signature compaction technique; small look-up table; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Computer simulation; Fault detection; Polynomials; Table lookup; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1999 IEEE Canadian Conference on
  • Conference_Location
    Edmonton, Alberta, Canada
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-5579-2
  • Type

    conf

  • DOI
    10.1109/CCECE.1999.807257
  • Filename
    807257