A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase dual-rail protocol

Author

Ruizhen Wu ; Yintang Yang ; Li Zhang

Author_Institution

Sch. of Microelectron., Xidian Univ., Xi´an, China

fYear

2013

fDate

11-14 Aug. 2013

Firstpage

503

Lastpage

506

Abstract

Asynchronous circuits have the advantages of high speed and low power consumption, but they can not work together with the synchronous module, thus synchronous and asynchronous packaging circuits become the research focus in GALS(globally asynchronous locally synchronous) bus systems. In this paper, a synchronous and asynchronous packaging circuit of asynchronous arbiters under four-phase dual-rail protocol is designed based on the standard gates. Verifications of the packaging circuit are implemented on Xilinx Viretex5 of 65nm CMOS technology. The results show that the power decreased by 88.3%, the working speed of synchronous-to-asynchronous module increased by 55.4%, and the working speed of asynchronous-to-synchronous module increased by 61.4% compared with the traditional suspended clock packaging circuits.

Keywords

CMOS digital integrated circuits; asynchronous circuits; integrated circuit packaging; low-power electronics; protocols; CMOS technology; GALS bus systems; Xilinx Viretex5; asynchronous arbiters; asynchronous packaging circuit; four-phase dual-rail protocol; globally asynchronous locally synchronous bus systems; size 65 nm; standard gates; suspended clock packaging circuits; synchronous packaging circuit; Asynchronous circuits; Encoding; Packaging; Power demand; Protocols; Standards; Synchronization; four-phase and dual-rail protocol; high-speed; low-power; packaging circuits; standard gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2013 14th International Conference on

Conference_Location

Dalian

Type

conf

DOI

10.1109/ICEPT.2013.6756521

Filename

6756521