A high throughput architecture for channel equalization based on a neural network using a wave pipeline method

Author

Morin, Frédéric ; Vidal, Martin ; Massicotte, Daniel

Author_Institution

Dept. of Electr. Eng., Quebec Univ., Trois-Rivieres, Que., Canada

Volume

1

fYear

1999

fDate

9-12 May 1999

Firstpage

560

Abstract

The use of a wave pipelining method for the design of a systolic architecture dedicated to channel equalization is proposed. A description is given of the piecewise linear multilayer neural network (PL-MNN) algorithm and the architecture. To improve the throughput of the architecture we propose a wave-pipelined version of the multiplier-accumulator (MAC) the presents the bottleneck of the architecture. A 16/spl times/8-bit MAC is performed using a normal process complementary pass transistor (NPCPL) as a universal cell for the creation of conventional logic gates and is used to optimize the wave pipelined MAC. The throughput and the latency of the MAC have been evaluated at 650 MHz and 8 ns respectively. The performance has been evaluated in a 0.5 /spl mu/m CMOS technology in comparison with the systolic architecture with and without a conventional pipeline and the proposed wave pipeline structure.

Keywords

CMOS logic circuits; VLSI; equalisers; logic gates; multilayer perceptrons; multiplying circuits; parallel algorithms; piecewise linear techniques; pipeline processing; systolic arrays; 0.5 mum; 16 bit; 650 MHz; 8 bit; 8 ns; CMOS technology; PL-MNN algorithm; VLSI; channel equalization; high throughput architecture; logic gates; multiplier-accumulator; neural network; normal process complementary pass transistor; performance evaluation; piecewise linear multilayer neural network; systolic architecture; universal cell; wave pipeline method; wave pipelined MAC; CMOS logic circuits; CMOS technology; Delay; Design methodology; Logic gates; Multi-layer neural network; Neural networks; Piecewise linear techniques; Pipeline processing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1999 IEEE Canadian Conference on

Conference_Location

Edmonton, Alberta, Canada

ISSN

0840-7789

Print_ISBN

0-7803-5579-2

Type

conf

DOI

10.1109/CCECE.1999.807260

Filename

807260