An ultra-low power charge-pump PLL with high temperature stability in 130 nm CMOS

An ultra-low power fully-integrated frequency synthesizer was designed and implemented in 130 nm CMOS technology. Based on integer-N phase locked loop architecture, the frequency synthesizer operates from 13.8 to 61 MHz. Current consumption has been minimized by the use of a mix of analog and digital blocks and a prior planning of current distribution amongst each blocks. The measured phase noise is -89.6 dBc/Hz @ 500 kHz offset and the current consumption is 77μA from 1.2V supply at 32MHz output. The reference frequency of 1MHz is generated from an on-chip RC based oscillator whose output frequency varies by only ±0.025% when temperature varies between -10°C to 110°C.