Abstract :
Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance. In this paper we designed a circuit switched NoC and compared that with packet switched NoC. By speculation and analysis, we propose that, as packet size increases, performance decreases for packet switched NoC, while it increases for circuit switched NoC. By close examination on the router architecture, we suggest that circuit switched NoC can operate at a higher clock frequency than packet switched NoC, and thus at zero load above a certain packet size circuit switched NoC could be better than packet switched NoC in packet delay. Experiment results support our intuitions and analysis. We find the cross-over point, above which circuit switching has lower latency, is around 30 flits/packet under low load and 60-70 flits/packet under high network load.
Keywords :
circuit complexity; circuit switching; clocks; integrated circuit design; network routing; network-on-chip; packet switching; circuit switched NoC analysis; circuit switched NoC design; circuit switched NoC evaluation; clock frequency; cross-over point; energy efficiency; hardware complexity; latency; network load; network-on-chip; packet delay; packet size; packet switched NoC analysis; packet switched NoC evaluation; router architecture; setup time; throughput; Clocks; Data transfer; Probes; Resource management; Switches; Switching circuits;
