A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints

This paper presents a new methodology for hardware accelerator generation, in the context of High Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) components. The very high computing capacity available in the latest FPGA makes them choice targets in High-Performance Computing (HPC) as well as embedded systems. For a much wider adoption of FPGA as general-purpose computing devices, the proposed HLS design flow leverages the users from all issues related to circuit structure fine-tuning. The HLS methodology is autonomous and produces RTL descriptions quickly, under only global resource and frequency constraints. This is achieved by performing incremental transformations of the input design description. The low complexity of the Design Space Exploration (DSE) algorithm and its good usage of all internal circuit structure constraints, make this HLS methodology very fast and able to generate pertinent solutions. Moreover, the generated circuit is designed to fit into the targeted FPGA or a given partition of it. Such a methodology leads to autonomous, fast and transparent DSE, all these issues known to limit the use of HLS and FPGA. Results on several benchmarks highlight the capabilities of our DSE methodology. The results show a high generation speed-up compared to other existing HLS approaches, while preserving correct performance of the generated circuits.