• DocumentCode
    3479852
  • Title

    Cache-Processor Coupling: A Fast & Wide On-Chip Data Cache Design

  • Author

    Motomura, M. ; Inoue, T. ; Yamada, Hiroyoshi ; Konagaya, A.

  • Author_Institution
    NEC Corporation, Japan
  • fYear
    1994
  • fDate
    9-11 June 1994
  • Firstpage
    69
  • Lastpage
    70
  • Keywords
    Added delay; Bandwidth; Circuit simulation; Coupling circuits; Decoding; National electric code; Radio frequency; Registers; Synthetic aperture sonar; Virtual private networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-1918-4
  • Type

    conf

  • DOI
    10.1109/VLSIC.1994.586220
  • Filename
    586220
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3479852