An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms

As mesh topology NoC is becoming a standard for implementing multi-core and multi-processor SoCs, there is a focus on developing routing algorithms for efficient on-chip communication. Junction Based Routing (JBR) is one such routing algorithm suitable for large NoC platforms. In this paper, we describe a router architecture as well as its FPGA prototyping for supporting the new routing algorithm. The router architecture required is much more complex because of the need of a routing table in each router and requires more complicated control to manage flow of packets through the router. Router design is described in detail and has a flit latency of only two clock cycles at zero load. The router design was prototyped using ALTERA DE2 board. We present FPGA utilization results for the router design and show that it is feasible to prototype large NoC platforms on available FPGA chips using our router design.