Title :
A Staggered Nand Dram Array Architecture For A Gbit Scale Integration
Author :
Shiratake, S. ; Takashima, D. ; Hasegawa, T. ; Nakano, H. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K. ; Masuoka, F.
Author_Institution :
Research and Development Center, TOSHIBA Corporation
Keywords :
Capacitance; Charge transfer; Degradation; Noise level; Random access memory; Research and development; Voltage;
Conference_Titel :
VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1918-4
DOI :
10.1109/VLSIC.1994.586223
