A Staggered Nand Dram Array Architecture For A Gbit Scale Integration

Author

Shiratake, S. ; Takashima, D. ; Hasegawa, T. ; Nakano, H. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K. ; Masuoka, F.

Author_Institution

Research and Development Center, TOSHIBA Corporation

fYear

1994

fDate

9-11 June 1994

Firstpage

Lastpage

Keywords

Capacitance; Charge transfer; Degradation; Noise level; Random access memory; Research and development; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1918-4

Type

DOI

10.1109/VLSIC.1994.586223

Filename

586223

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