Title :
A systolic architecture for channel equalization based on a piecewise linear fuzzy logic algorithm
Author :
Zakhama, Mourad ; Massicotte, Daniel
Author_Institution :
Electr. Eng. Dept., Quebec Univ., Trois-Rivieres, Que., Canada
Abstract :
A systolic architecture dedicated to a piecewise linear fuzzy logic algorithm for a nonlinear channel equalization is presented. The piecewise linear membership function proposed for the inference step is more suitable for a VLSI implementation than the Gaussian function proposed in the literature. Depending on the number of piecewise linear membership functions (m) on the input space, the equalizer can perform for linear or nonlinear channel equalization. The performance evaluation of the systolic architecture is evaluated in terms of speed and area. The latency and throughput of the 16-bits design are respectively (2m+1)f/sub c/ and f/sub c/, where f/sub c/ is the clock frequency. In 0.5 /spl mu/m CMOS technology the f/sub c/ is evaluated at 40 MHz.
Keywords :
CMOS logic circuits; VLSI; equalisers; fuzzy logic; piecewise linear techniques; systolic arrays; 0.5 mum; 16 bit; 40 MHz; CMOS technology; Gaussian function; VLSI implementation; area; clock frequency; inference step; input space; latency; linear channel equalization; nonlinear channel equalization; performance evaluation; piecewise linear fuzzy logic algorithm; piecewise linear membership function; speed; systolic architecture; throughput; CMOS technology; Clocks; Delay; Equalizers; Frequency; Fuzzy logic; Inference algorithms; Piecewise linear techniques; Throughput; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 1999 IEEE Canadian Conference on
Conference_Location :
Edmonton, Alberta, Canada
Print_ISBN :
0-7803-5579-2
DOI :
10.1109/CCECE.1999.808205
