Title :
MAX EPLD Family: PAL Speed to FPGA Density
Author_Institution :
Altera Corporation
Keywords :
Clocks; Feeds; Field programmable gate arrays; Flip-flops; Logic arrays; Logic devices; Macrocell networks; Packaging; Plastics; Programmable logic arrays;
Conference_Titel :
Electro International, 1991
Conference_Location :
New York, NY, USA
DOI :
10.1109/ELECTR.1991.718235
