DocumentCode
3480262
Title
Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v
Author
Akioka, T. ; Yukutake, S. ; Fukui, K. ; Mitsumoto, K. ; Hiraishi, A. ; Nakagawa, K. ; Akiyama, N. ; Iwamura, M. ; Kobayashi, Y. ; Ikeda, S. ; Uchida, H.
Author_Institution
Hitachi Research Laboratory, Hitachi Ltd., Hitachi, Ibaraki, Japan
fYear
1994
fDate
9-11 June 1994
Firstpage
111
Lastpage
112
Keywords
BiCMOS integrated circuits; Bipolar transistors; Circuit simulation; Delay; Laboratories; Parasitic capacitance; Photonic band gap; Random access memory; Temperature dependence; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-1918-4
Type
conf
DOI
10.1109/VLSIC.1994.586241
Filename
586241
Link To Document