Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder

This paper describes the architecture of the high-throughput interpolator used in motion estimation and compensation of the HEVC encoder. The architecture reads eight input samples and produces 64 output samples at each clock cycle. Two versions are developed for FGPA and ASIC technologies. Synthesis results show that they can operate at 200 and 400 MHz when implemented in FPGA Aria II and TSMC 130 nm, respectively. This enables encoders to support HD resolutions. The paper also analyzes relation between compression efficiency and hardware complexity of the interpolation in HEVC and H.264/AVC.