Title :
A 2.6-ns Wave-pipelined Cmos Sram With Dual-sensing-latch
Author :
Tachibana, S. ; Higuchi, H. ; Takasugi, K. ; Sasaki, K. ; Yamanaka, T. ; Nakagome, Y.
Author_Institution :
Central Research Laboratory, Hitachi, Ltd.,
Keywords :
Capacitance; Circuits; Clocks; Delay effects; Latches; Random access memory; Synchronization; Temperature dependence; Throughput; Voltage;
Conference_Titel :
VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1918-4
DOI :
10.1109/VLSIC.1994.586244
