A 2.6-ns Wave-pipelined Cmos Sram With Dual-sensing-latch

Author

Tachibana, S. ; Higuchi, H. ; Takasugi, K. ; Sasaki, K. ; Yamanaka, T. ; Nakagome, Y.

Author_Institution

Central Research Laboratory, Hitachi, Ltd.,

fYear

1994

fDate

9-11 June 1994

Firstpage

117

Lastpage

118

Keywords

Capacitance; Circuits; Clocks; Delay effects; Latches; Random access memory; Synchronization; Temperature dependence; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1918-4

Type

DOI

10.1109/VLSIC.1994.586244

Filename

586244

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