An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects

This paper presents a novel methodology to provide a promising solution for complex on-chip communication problems in order to reduce power consumption and delay. Our proposed reconfigurable Network-on-Chip (NoC) architecture is integrated with the radio frequency Interconnect (RF-I) with signal propagation at the speed of light. It is based on setting up express shortcut paths (ESPs) which include single-cycle multi-hop RF-I shortcut between selected pairs of NoCs cores. Hence, the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these ESPs. In this scheme, ESPs are constructed based on an energy model and performance constraints to accelerate critical communication path at the design time. Further, we also try to optimize these ESPs by using a novel flow control at a run time. Additionally, a suitable routing algorithm is suggested to support the packet to reach their destinations appropriately without struggling in congested paths. The experimental results captured by SoCs applications reveal that in comparison with the conventional NoC router, the proposed router takes 49% and 74% reduction in latency and energy, respectively besides 8.7% area overhead.