Simultaneous switching noise considerations in the design of a high speed, multiported TLB of a server-class microprocessor

Noise introduced on the supply networks by simultaneous switching of the nodes of complex macros is becoming an important issue in very deep sub-micron technologies. Server-class microprocessors demand design of very high speed multiported macros that generate high peak currents and current slew-rates. This paper investigates one such macro: a fully-associative, multiported data TLB. Our simulations show a slowdown of 10-20% due to the supply noise despite robust C4-based supply network. The traditional solution of employing decoupling capacitors to combat the supply noise results in an unacceptable area increase. Macro design techniques that can reduce peak current and current slew rate without reducing the speed of critical path are proposed. Employment of hierarchical match line and delayed split precharge techniques reduce the SSN and the required decoupling capacitance by a factor of 5x