Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers

This work describes FPGA hardware architectures of GF(2^m) multipliers being more compact than a bit-serial multiplier and outperforming software counterparts. The proposed multiplier is more compact than a hardware implementation of the bit-serial approach, considered the most compact one. Also, the designs proposed still outperform software counterparts. For field multiplication, the multiplicand and modulus are parsed in digits of size d while the multiplier is parsed in digits of size D. Thus, the area complexity of the multiplier is mainly determined by the digits {D, d}, not by the order of the finite field m, which affects only the latency and thus the throughput. This approach allows to implement GF(2^m) multipliers for any finite field with practically the same amount of FPGA resources. Several multiplier versions were implemented using different combinations for {D, d} in order to find the most compact designs while achieving better performance and efficiency than a bit-serial multiplier. From a hardware implementation in the xc3s1500 FPGA for the finite field GF(2²³³), the most efficient multiplier is obtained using the digits {D=6, d= 12}, requiring 70% less area resources than a bit-serial multiplier.