DocumentCode :
3480898
Title :
Interfacial delamination analysis at chip/underfill interface and investigation of its effect on flip-chip´s reliability
Author :
Xiang Gao ; Fei Wang ; Sheng Liu
Author_Institution :
Div. of MOEMS, Huazhong Univ. of Sci. & Technol., Wuhan, China
fYear :
2013
fDate :
11-14 Aug. 2013
Firstpage :
954
Lastpage :
958
Abstract :
Flip-chip packaging on organic substrate has been used widely as a promising package technology for the next generation of electronic devices. However, due to its numerous interfaces (i.e. die/passivation, passivation/underfill, underfill/solder mask, and solder mask/circuit board), it is more susceptible to a variety of complexworking and testing environments, delamination can easily take place in some critical sites, which is one of the greatest threats to its reliability. In this paper, delamination initiation and propagation behaviors of horizontal and vertical chip/underfill interfaces under temperature cycling tests are analyzed respectively by using cohesive zone model (CZM). The results indicate that delamination will occur first along the horizontal interface between chip and underfill and even when it propagates about 0.13mm, delamination still have not taken place at vertical interface. What´s more, variance of phase angle with testing time and crack length is investigated. It turns out that when the crack is short, shearing stress dominates the contribution to causing the interfacial delamination, however, when the crack becomes long, the peeling stress gradually turns to be in the same range or even higher than that of shearing stress. Compared with interfacial delamination in vertical direction, the horizontal one induces a bigger threat to the reliability of flip-chip package because once it propagates to the solder joints, the fatigue life of solder would be reduced rapidly. The effect of interfacial delamination on fatigue life of solders is also implemented in this paper. It is found that plastic strain has been more than doubled in one temperature cycle when interfacial delamination is induced. Fatigue life is estimated by using modified Coffin-Mansin equation. It is found that induced interfacial delamination can decrease the solder´s life by about 93.5%. Furthermore, the imperfection of underfill layers and some voids in the corners of the so- der joints caused by the contamination of the flux residues in the corners of the solder joints are also taken into account. And the incremental inelastic strain caused by the voids is compared with that induced by interfacial delamination. It is found that interfacial delamination can lead to much higher plastic strain, that is to say, compared with process-induced defects, delamination has a much greater impact on solder´s fatigue life and the whole package´s reliability.
Keywords :
delamination; fatigue cracks; flip-chip devices; integrated circuit reliability; organic semiconductors; plastic deformation; solders; substrates; CZM; cohesive zone model; crack length; critical sites; delamination initiation; electronic devices; flip-chip packaging; horizontal chip; horizontal interface; incremental inelastic strain; interfacial delamination; modified Coffin-Mansin equation; organic substrate; package technology; peeling stress; phase angle variance; plastic strain; propagation behaviors; reliability; shearing stress; solder fatigue life; solder joints; temperature cycle; temperature cycling tests; testing time; underfill interfaces; underfill layers imperfection; vertical chip; vertical interface; Delamination; Fatigue; Flip-chip devices; Reliability; Soldering; Strain; Stress; Flip-chip; fatigue life; interfacial delamination; reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2013 14th International Conference on
Conference_Location :
Dalian
Type :
conf
DOI :
10.1109/ICEPT.2013.6756618
Filename :
6756618
Link To Document :
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