DocumentCode :
348090
Title :
Conceptual modeling and simulation
Author :
Cyre, Walling R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
fYear :
1999
fDate :
1999
Firstpage :
293
Lastpage :
296
Abstract :
System-level design requires behavioral models of its complex components in order to validate the designs, synthesize implementations and generate tests. Descriptions of these components are often only available as English descriptions. Developing behavioral models from natural language descriptions has been a tedious and time consuming task. The paper describes the semiautomatic generation of conceptual models from text and a simulator for these models. The conceptual modeling language is a knowledge representation notation (semantic hypergraphs), and simulation of these abstract descriptions based on the VHDL execution model is described. Simulation at the conceptual level avoids having to add the extraneous declarations and other syntactic artifacts necessary with more conventional description languages. These declarations not only take time, but also prejudice the implementation
Keywords :
circuit simulation; hardware description languages; natural languages; semantic networks; VHDL execution model; abstract descriptions; behavioral models; complex components; conceptual modeling; conceptual modeling language; knowledge representation notation; natural language descriptions; semantic hypergraphs; semiautomatic generation; simulator; syntactic artifacts; system-level design; Computational linguistics; Data mining; Design engineering; Humans; Natural languages; Proposals; Read only memory; System testing; Tellurium; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 1999. (ICCD '99) International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-0406-X
Type :
conf
DOI :
10.1109/ICCD.1999.808552
Filename :
808552
Link To Document :
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