Groove structure for stress releasing around TSV

Author

Han Sun ; Yudan Pi ; Wei Wang ; Jing Chen ; Yufeng Jin

Author_Institution

Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China

fYear

2013

fDate

11-14 Aug. 2013

Firstpage

965

Lastpage

967

Abstract

Through silicon via (TSV) is one of the most significant techniques in microelectronic packaging. In 3 dimensional integrated circuit (3D IC), TSV brings great performance improvement and high density device integration. Meanwhile, the usage of copper in TSV causes serious thermal stress issue, which considerably affects the device performance and reliability. This paper proposed a unique structure to release TSV-induced stress. Numerical simulation was used to study the stress distribution around the TSV and optimize the geometric parameters, including the depth, width and position of the proposed stress-releasing groove.

Keywords

integrated circuit design; integrated circuit packaging; integrated circuit reliability; thermal stresses; three-dimensional integrated circuits; 3 dimensional integrated circuit; 3D IC; TSV-induced stress; copper; device performance; device reliability; geometric parameters; high density device integration; microelectronic packaging; stress distribution; stress-releasing groove; thermal stress issue; through silicon via; Copper; Silicon; Stress; Substrates; Thermal stresses; Through-silicon vias; Stress-releasing Groove; TSV; Thermal stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2013 14th International Conference on

Conference_Location

Dalian

Type

conf

DOI

10.1109/ICEPT.2013.6756620

Filename

6756620