DocumentCode
34811
Title
Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests
Author
Pomeranz, Irith
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
33
Issue
12
fYear
2014
fDate
Dec. 2014
Firstpage
1955
Lastpage
1964
Abstract
This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, trem and tmod, with sets of detected faults Drem and Dmod, respectively. Starting from tnew = tmod, and considering tnew as a variation of trem, the procedure restores bits of trem into tnew as necessary to ensure that faults from Drem are detected by tnew. The procedure then restores bits of tmod into tnew as necessary to ensure that all the faults from Dmod are detected by tnew. The test tnew is used for replacing tmod, and the faults it detects out of Drem are moved to Dmod. After several such steps, if Drem becomes empty, trem can be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification.
Keywords
boundary scan testing; fault simulation; detected faults; restoration procedure; scan circuits; static test compaction; test modification; test removal; test set; Circuit faults; Compaction; Testing; Broadside tests; restoration procedure; skewed-load tests; static test compaction; transition faults;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2358932
Filename
6951452
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