Modeling yield throughout the DRAM product life cycle

This paper presents a modeling technique for predicting DRAM die-per-wafer yield throughout a product´s fabrication life cycle. Using manufacturing yield data, it is shown that an accurate mature yield prediction for a wide range of product types can be made by modifying the standard Poisson yield model to account for defect clustering, minimum dimension, and process complexity. It is also shown that an invariable learning factor can be derived using a learning curve equation based on average fabrication cycle time. This derivation leads to an accurate yield forecast through time