Studies on reliability of a 3D system-in-package device

To meet the needs of multifunction and miniaturization of modern electronic products, system-in-package (SiP) has been adapted as one of the most promising packaging technologies. It integrates different chips and devices into one package, which greatly reduces the package size and enhances the performance. However, the relatively complex structure of SiP may cause unexpected failure to the solder joints or silicon chips. In this paper, a 3D package with one larger chip on an FR4 board and four smaller chips on the back side was designed to study the reliability of SiP. The chips were flip-chip bonded to the FR4 board and experienced a set of reliability tests including thermal shock and drop test under JEDEC standards. Moreover, underfill was applied to enhance the reliability of the SiP. The effect of the multiple reflow processes for assembling the complex 3D sample on the reliability of SiP was examined. Failure analysis was carried out to find out the failure mechanism.