Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques

Digital circuits exposed to environments with high levels of radiation, such as those found in High Energy Physics experiments, are prone to Single Event Upsets. These upsets impact the reliability of the circuit. In order to mitigate the effects of the upsets, several well-known techniques for use with register transfer level (RTL) circuit descriptions have been proposed over the years. They typically have a large impact on circuit size and power consumption. Therefore, they are often applied only to the more critical modules of the system. Additionally, the manual implementation of those techniques has a significant cost in terms of time and design effort, involving both RTL changes and tailoring of the synthesis flow to avoid optimizing away the additional hardware. This paper describes an automated workflow that reduces the time for implementing SEU mitigation techniques, avoids the errors caused by manual alteration of the RTL descriptions, and enables the designer to explore different alternatives quickly. The paper describes the application of the workflow to three digital circuits and discusses the data obtained from the implementation of the different mitigation techniques.