• DocumentCode
    3481767
  • Title

    Runtime Online Links Voltage Scaling for Low Energy Networks on Chip

  • Author

    Mineo, Andrea ; Palesi, Maurizio ; Ascia, Giuseppe ; Catania, Vincenzo

  • Author_Institution
    Univ. of Catania, Catania, Italy
  • fYear
    2013
  • fDate
    4-6 Sept. 2013
  • Firstpage
    941
  • Lastpage
    944
  • Abstract
    The power dissipated by the links of a network on chip (NoC) accounts for a significant fraction of the overall power budget. Reducing the operating voltage of the network links, results in a square reduction of their power contribution. Unfortunately, the voltage reduction has a negative impact on communication reliability in terms of bit error rate. Starting from the assumption that not all the communications require the same reliability level, we present a technique for dynamically changing the voltage of the links based on the communication reliability requirements. The experiments, carried out under both synthetic and real traffic scenarios, show the effectiveness of the proposed technique which allows to save up of 55% of link energy with a total energy saving of 25% of the entire NoC.
  • Keywords
    integrated circuit reliability; network-on-chip; power aware computing; NoC; bit error rate; communication reliability; communication reliability requirements; low energy networks-on-chip; network links; operating voltage reduction; overall power budget; power contribution square reduction; runtime online links voltage scaling; Bit error rate; Logic gates; Quality of service; Robustness; Streaming media; Transceivers; Link power reduction; Low power; Network on Chip; Power analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design (DSD), 2013 Euromicro Conference on
  • Conference_Location
    Los Alamitos, CA
  • Type

    conf

  • DOI
    10.1109/DSD.2013.106
  • Filename
    6628379