Reduction of signal reflection caused by TSV insertion in three-dimensional on-chip high speed interconnect lines

Characteristic impedance of Through Silicon Via (TSV) differs from the transmission lines´ in high speed three-dimensional integrated circuits (3D ICs), resulting in signal reflection and degrading the signal quality. We add a capacitance to the connection of TSV and interconnects to reduce the TSV-induced signal reflection in multilevel interconnect structures for frequencies up to gigascale. Simulation result indicates that the signal reflection can be weakened obviously from -3 dB to -25 dB with the help of matching capacitance, using S-parameter analysis in the technology of 65 nm node. For different circuits, we can choose appropriate matching capacitance to minimize the signal reflection according to the circuit parameters.