Low power floating point MAFs-a comparative study

Author

Pillai, R.V.K. ; Shah, S.Y.A. ; Al-Khalili, A.J. ; Al-Khalili, D.

Author_Institution

StarCore Technol. Centre, Agere Syst., Atlanta, GA, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

284

Abstract

We present a comparative study of three data path architectures for floating point multiply-accumulate fusion. Power/delay behavior of two new MAFs are compared with that of a modified IBM MAF. The functional partitioning of the new MAFs into four distinct, clock gated modules allows activity reduction. The switching activity function of the new MAFs is represented as a four state FSM. During any given operation cycle, only one of the data path modules is active, during which occasion, the logic assertion status of the circuit nodes of the other modules are maintained at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and data path simplifications. The new MAFs offer worst case power reductions in excess of 15% with FPGA realization while the corresponding figure for 0.35 micron CMOS process is better than 26%

Keywords

CMOS logic circuits; field programmable gate arrays; finite state machines; floating point arithmetic; CMOS process; FPGA realization; clock gated modules; critical path delay; data path architectures; floating point multiply-accumulate fusion; four state FSM; functional partitioning; latency; logic assertion status; power/delay behavior; speculative rounding; switching activity function; Circuit synthesis; Clocks; Delay; Educational institutions; Field programmable gate arrays; Logic circuits; Power engineering and energy; Power engineering computing; Power measurement; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and its Applications, Sixth International, Symposium on. 2001

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-6703-0

Type

conf

DOI

10.1109/ISSPA.2001.949833

Filename

949833