Investigations of symbol synchronization implementation for 2×2 MIMO system using FPGA

This paper has reported on the design and development of an FPGA based 2times2 MIMO testbed employing commercially available MAX289 RF transceiver chips and in-house developed antennas. Details of the operation of various parts of this system have been described. A particular attention has been paid to symbol synchronization which is crucial to achieving the data demodulation, channel estimation, and data decoding. It has been shown that symbol synchronization can be accomplished by comparing the I and Q signals on a short sequence of data. The validity of this approach has investigated on data obtained from direct wire connection on the baseband and RF level as well as RF signals sent through air with antennas.