On The Design Of Fault Tolerant Systolic Array For Fuzzy Logic

For fast fuzzy inference processes in fuzzy control systems, a systolic VLSI array has been reported. Due to their complexity, VLSI circuits including systolic array sometimes fail, and the result is an erroneous output. In this paper, fault detection capability is added to the systolic array that performs fast fuzzy inference processes. The design described is based on the duplication with complementary logic technique. Minimal additional hardware is needed for each processing element, Fuzzy Inference Step Processor (FISP), in the systolic array.