VHDL-based methodology for modelling computer communication systems

Currently the design and development process employs different modelling and design techniques at each level of system abstraction. This makes the process inefficient and costly. VHDL, however, has the potential to unify this process. VHDL´s widespread use in the design, development and synthesis of ASICs is an indication of its success. It has already lead to revolutionary changes in the way traditional systems design is performed. Today new ASIC design starts with a VHDL description of the circuit and then the ASIC is synthesized from this description. The next step in VHDL´s evolutionary use is in the modelling of systems at higher levels of abstraction. The specification and design of an entire large scale system is possible. This paper presents a VHDL-based methodology for modelling computer communication systems, called VCCS, to demonstrate VHDL´s ability to design and model systems at a high level of abstraction. The methodology, design strategy and primary characteristics of the VHDL implementation are explained