A flexible multi-channel high-resolution time-to-digital converter ASIC

Author

Mota, M. ; Christiansen, J. ; Débieux, S. ; Ryjov, V. ; Moreira, P. ; Marchioro, A.

Author_Institution

CERN, Geneva, Switzerland

Volume

2

fYear

2000

fDate

2000

Abstract

A data driven multi-channel time-to-digital converter (TDC) circuit with programmable resolution (~25 ps-800 ps binning) and a dynamic range of 102.4 μs has been implemented in a 0.25 μm CMOS technology. An on-chip PLL is used for clock multiplication up to 320 MHz from an external 40 MHz reference. A 32 element delay locked loop (DLL) performs time interpolation down to 97.5 ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5 ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation

Keywords

CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; delay lines; delay lock loops; nuclear electronics; phase locked loops; 0.25 μm CMOS technology; 320 MHz; 40 MHz; TDC; adjustable on-chip RC delay line; clock multiplication; delay locked loop; flexible multichannel time-to-digital converter; high-resolution time-to-digital converter ASIC; phase locked loop; programmable resolution; Application specific integrated circuits; Buffer storage; CMOS technology; Clocks; Delay lines; Detectors; Interpolation; Microelectronics; Phase locked loops; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2000 IEEE

Conference_Location

Lyon

ISSN

1082-3654

Print_ISBN

0-7803-6503-8

Type

conf

DOI

10.1109/NSSMIC.2000.949889

Filename

949889