Title :
Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap
Author :
Moll, H.-P. ; Hartwich, J. ; Scholz, A. ; Temmler, D. ; Graham, A.P. ; Slesazek, S. ; Wedler, G. ; Heineck, L. ; Mono, T. ; Zimmermann, U. ; Schupke, K. ; Ludwig, F. ; Park, I. ; Tran, T. ; Müller, W.
Author_Institution :
Qimonda Dresden GmbH & Co. OHG, Dresden
Abstract :
We report an enabling technology for 40 nm trench DRAM and beyond. The 3-dimensional array transistor is formed self-aligned (SA) to the deep trench (DT) capacitor; and the single-sided strap contact (SC) connecting the array transistor to the trench capacitor is formed self-aligned within the deep trench. This technology eliminates critical lithography levels and provides robust process windows for DRAM trench cell scaling to below 40 nm.
Keywords :
DRAM chips; capacitors; isolation technology; transistors; 3D array transistor; lithography levels; self-alignment techniques; single-sided strap; size 40 nm; trench capacitor DRAM technologies; Capacitors; Contact resistance; Implants; Joining processes; Lithography; MONOS devices; Random access memory; Robustness; Scattering; Wet etching;
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
DOI :
10.1109/VLSIT.2007.4339687
