Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V_T NMOS and PMOS devices with 725/370 muA/mum (at V_DD=1.1 V, I_off=20 pA/mum and J_g= 100/1 mA/cm²). We demonstrate that adding embedded Si_0.75Ge_0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V_T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni₃₁Si₁₂ or Ni₂Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: -shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; -extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.