DocumentCode
3484689
Title
Management of Power and Performance with Stress Memorization Technique for 45nm CMOS
Author
Eiho, A. ; Sanuki, T. ; Morifuji, E. ; Iwamoto, T. ; Sudo, G. ; Fukasaku, K. ; Ota, K. ; Sawada, T. ; Fuji, O. ; Nii, H. ; Togo, M. ; Ohno, K. ; Yoshida, K. ; Tsuda, H. ; Ito, T. ; Shiozaki, Y. ; Fuji, N. ; Yamazaki, H. ; Nakazawa, M. ; Iwasa, S. ; Murama
Author_Institution
Toshiba Corp., Yokohama
fYear
2007
fDate
12-14 June 2007
Firstpage
218
Lastpage
219
Abstract
The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.
Keywords
CMOS integrated circuits; semiconductor technology; stress effects; CMOS; mobility enhancement; power management; power reduction; size 45 nm; stress memorization technique; CMOS technology; Capacitive sensors; Energy management; Gate leakage; Germanium silicon alloys; Grain size; Silicon germanium; Substrates; Surface-mount technology; Tensile stress;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-03-1
Type
conf
DOI
10.1109/VLSIT.2007.4339699
Filename
4339699
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