Author :
Eiho, A. ; Sanuki, T. ; Morifuji, E. ; Iwamoto, T. ; Sudo, G. ; Fukasaku, K. ; Ota, K. ; Sawada, T. ; Fuji, O. ; Nii, H. ; Togo, M. ; Ohno, K. ; Yoshida, K. ; Tsuda, H. ; Ito, T. ; Shiozaki, Y. ; Fuji, N. ; Yamazaki, H. ; Nakazawa, M. ; Iwasa, S. ; Murama
Abstract :
The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.
Keywords :
CMOS integrated circuits; semiconductor technology; stress effects; CMOS; mobility enhancement; power management; power reduction; size 45 nm; stress memorization technique; CMOS technology; Capacitive sensors; Energy management; Gate leakage; Germanium silicon alloys; Grain size; Silicon germanium; Substrates; Surface-mount technology; Tensile stress;
