Author :
Yin, Haizhou ; Sung, C.Y. ; Saenger, K.L. ; Hamaguchi, M. ; Hasumi, R. ; Ohuchi, K. ; Ng, H. ; Zhang, R. ; Stein, K.J. ; Wallner, T.A. ; Li, J. ; Ott, J.A. ; Chen, X. ; Luo, Z.J. ; Rovedo, N. ; Fogel, K. ; Pfeiffer, G. ; Kleinhenz, R. ; Bendernagel, R. ;
Abstract :
When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.
Keywords :
elemental semiconductors; integrated circuit bonding; silicon; solid phase epitaxial growth; DSB; direct silicon bonded technology; shallow trench isolation; size 32 nm; solid phase epitaxy; Bonding; CMOS technology; Degradation; Epitaxial growth; Implants; Isolation technology; Scalability; Silicon; Solids; Substrates;
