Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Author

Kwak, Donghwa ; Park, Jaekwan ; Kim, Keonsoo ; Yim, Yongsik ; Ahn, Soojin ; Park, Yoonmoon ; Kim, Jinho ; Jeong, Woncheol ; Kim, Jooyoung ; Park, Mincheol ; Yoo, Byungkwan ; Song, Sangbin ; Kim, Hyunsuk ; Sim, Jaehwang ; Kwon, Sunghyun ; Hwang, Byungjoon

Author_Institution

Samsung Electron. Co, Ltd,, Hwasung

fYear

2007

fDate

12-14 June 2007

Firstpage

12

Lastpage

13

Abstract

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO₂ /SiN/Al₂O₃/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

Keywords

NAND circuits; field effect transistor circuits; lithography; semiconductor storage; HCFET; NAND flash memory; breakthrough patterning technology; generation multi-level NAND flash; hemi-cylindrical FET; lithography; self aligned double patterning; size 38 nm; Aluminum oxide; Annealing; Contacts; Flash memory; Isolation technology; Lithography; Plasma temperature; Testing; Vehicles; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339707

Filename

4339707