Title :
High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology
Author :
Luo, Zhengqian ; Rovedo, N. ; Ong, S. ; Phoong, B. ; Eller, M. ; Utomo, H. ; Ryou, C. ; Wang, Huifang ; Stierstorfer, R. ; Clevenger, L. ; Kim, Sungho ; Toomey, J. ; Sciacca, D. ; Li, Jie ; Wille, W. ; Zhao, Lu ; Teo, L. ; Dyer, T. ; Fang, Shao-Yun ; YAN,
Author_Institution :
IBM Semicond. R&D Center, Hopewell Junction
Abstract :
An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.
Keywords :
CMOS integrated circuits; field effect transistor circuits; NFET; PFET; SRAM; advanced stressors integration; aggressively scaled bulk CMOS technology; high performance transistors; low-k back-end dielectric; size 45 nm; thermal processes; CMOS technology; DSL; Delay; Dielectrics; Lithography; Random access memory; Space technology; Thermal stresses; Transistors; Wiring;
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
DOI :
10.1109/VLSIT.2007.4339709
