Title :
Exploiting component/event-level parallelism in concurrent fault and design error simulation
Author :
Shaikh, Saghir A. ; Szygenda, Stephen A.
Author_Institution :
Level One Commun. Inc., Sacramento, CA, USA
Abstract :
The paper describes the algorithm CON2FERS, which exploits the event level and component level parallelisms in the concurrent technique for fault and design error simulation. This algorithm assumes asynchronous, message based operation with NORMA, and MIMD models of programming. A design verification tool based on this algorithm is developed with object oriented methodology using C++ and PVM. This implementation is executable on any Network of Workstations (NOW) and/or any general purpose parallel machine. The statistics on fault and error simulation performance and load balancing for some benchmark circuits are presented. Various experimental results of the effect of network and load on the performance of the CON2FERS, and the applicability of the algorithm for the hardware acceleration of CFES are also presented
Keywords :
digital simulation; logic CAD; message passing; object-oriented programming; parallel algorithms; parallel programming; performance evaluation; resource allocation; virtual machines; CFES; CON2FERS; MIMD models; NORMA; Network of Workstations; benchmark circuits; component level parallelism; component/event-level parallelism; concurrent algorithm; concurrent technique; design error simulation; design verification tool; error simulation performance; general purpose parallel machine; hardware acceleration; load balancing; message based operation; object oriented methodology; Algorithm design and analysis; Circuit faults; Circuit simulation; Discrete event simulation; Error analysis; Hardware; Load management; Object oriented modeling; Parallel machines; Workstations;
Conference_Titel :
Simulation Symposium, 1997. Proceedings., 30th Annual
Conference_Location :
Atlanta, GA
Print_ISBN :
0-8186-7934-4
DOI :
10.1109/SIMSYM.1997.586486
