Advanced electrical characterization toward (sub) 1nm EOT HfSiON - hole trapping in PFET and L-dependent effects

Hf-based gate dielectrics layers with EOT≪1nm are actively investigated for 22nm node and beyond. EOT scalability of these films is simultaneously achieved by reducing the high-k thickness as well as optimizing the N-profile into the thin film. For Hf-based layers electron traps in the upper part of the bandgap have been a major concern for nMOSFETs since they cause V_T-instability and affect mobility [1]. With the scaling of EOT to 1 nm and below, the impact of these traps has, however, disappeared [2]. Electron traps have never been considered a potential problem for PMOS because at negative bias they are always efficiently discharged. We found, however, that in PMOS with EOT ˜1 nm, a large hysteresis at high field is observed in the I_D-V_G characteristics, while no hysteresis is measured on the corresponding NMOS devices (on the same wafer) (Fig. 1). In this work we will prove by an advanced charge pumping technique that the hysteresis in PMOS is caused by hole traps in the high-k layer. Furthermore, we show how NBTI defects are correlated with such hole traps. Hole trap density depends on the Hf- and N-profile in the film, being larger for Hf-rich films.