Statistical modeling for a 0.6 μm BiCMOS technology

Author

Power, James A. ; Kelly, Sean C. ; Griffith, Edel C. ; Doyle, Denis ; Neill, Mike O.

Author_Institution

Analog Devices, Limerick, Ireland

fYear

1997

fDate

28-30 Sep 1997

Firstpage

24

Lastpage

27

Abstract

A methodology enabling the generation of accurate statistical circuit simulator (SPICE-level) parameter sets for a 0.6 μm BiCMOS process is described. Conventional MOS and BJT parameter extraction practices are too time-consuming to be a realistic option for the construction of the required statistical SPICE parameter database. In this work, accurate relationships are derived between E-Test (WAT) parameters and SPICE-level parameters. Typically E-Test data is routinely monitored and readily available while SPICE-level parameters are much more difficult and expensive to obtain

Keywords

BiCMOS integrated circuits; SPICE; integrated circuit modelling; 0.6 micron; BiCMOS technology; E-Test; SPICE; WAT; circuit simulation; parameter extraction; statistical model; BiCMOS integrated circuits; Circuit simulation; Condition monitoring; Databases; Equations; Implants; MOSFET circuits; Parameter extraction; Predictive models; Reflection; SPICE; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Conference_Location

Minneapolis, MN

ISSN

1088-9299

Print_ISBN

0-7803-3916-9

Type

conf

DOI

10.1109/BIPOL.1997.647348

Filename

647348