DocumentCode :
348526
Title :
Effect of energy reduction in sub-keV boron implantation on ultra-shallow junction formation
Author :
Yasunaga, T. ; Matsuda ; Shishiguchi, S. ; Saito, S.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Volume :
1
fYear :
1999
fDate :
1999
Firstpage :
18
Abstract :
Ultra-shallow junctions under 50 nm are required at source/drain (S/D) region for deep sub-quarter micron devices. Reduction in implantation energy has been an effective way for realizing shallower junctions, due to the elimination of transient enhanced diffusion (TED). However, the effect of energy reduction in sub-keV boron implantation has not been clarified. An additional diffusion-enhanced mechanism has been previously reported in this energy region. In addition, low beam current will be the problem to apply sub-keV implantation to device manufacturing. Decel mode implantation has been developed for increases in beam current; however, the influence on device performance has not been evaluated. In this work, we investigate the effect of implantation energy reduction on sub-micron PMOS-FETs and the device effect of energy contamination when using decel mode implantation. In this work, B was implanted into S/D extension regions at 0.2-0.5 keV, 5×1014 /cm2 by drift mode. After deep-S/D implantation, samples were annealed at 950°C for 10 sec. The junction depth was decreased from 31.2 nm down to 23 nm by reducing the B energy from 0.5 keV to 0.2 keV. This shows that the reduction of B energy is effective to realize shallower junction in sub-keV region. Threshold voltages (Vt) were measured for PMOS-FETs with gate length from 0.15 μm to 1 μm. The Lmin, which indicates the short channel effect, was improved 5% by the reduction of B energy from 0.5 keV to 0.2 keV. This shows that the energy reduction is also effective to decrease the B lateral diffusion at the short channel region. To investigate device effects of energy contamination at 0.5 keV implantation, B was implanted before the S/D extension implantation at 2-5 keV, 5×1012-2.5×10 13/cm2 as a 1-5% contamination element. We found that acceptable energy contamination is under 3% for 2 keV for 0.15 μm devices. And, 10% fluctuation of energy contamination at 2 keV 3% energy contamination is acceptable
Keywords :
MOS integrated circuits; MOSFET; annealing; boron; elemental semiconductors; ion implantation; semiconductor doping; semiconductor junctions; silicon; 0.2 to 0.5 keV; 950 degC; B energy; B lateral diffusion; Si:B; annealing; decel mode implantation; deep sub-quarter micron devices; device manufacturing; diffusion-enhanced mechanism; drift mode; energy contamination; energy reduction; gate length; implantation energy; junction depth; low beam current; short channel effect; source/drain region; sub-keV boron implantation; sub-micron PMOS-FETs; threshold voltages; transient enhanced diffusion; ultra-shallow junction formation; Annealing; Boron; Contamination; Implants; Length measurement; Manufacturing; National electric code; Pollution measurement; Threshold voltage; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ion Implantation Technology Proceedings, 1998 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4538-X
Type :
conf
DOI :
10.1109/IIT.1999.812041
Filename :
812041
Link To Document :
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