Title :
A complex multiplier using overturned-stairs adder tree
Author :
Li, Weidong ; Wanhammar, Lars
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
In this paper we describe a new complex multiplier based on Distributed Arithmetic (DA) using an overturned-stairs adder tree (OS-tree). The OS-tree yields the same speed as the optimal Wallace tree, but has the advantage of a regular layout. A 17×13 complex multiplier is implemented with MietecTM 0.35 μm standard CMOS technology. It can execute 30 Mmult./s and dissipate about 15 mW at 25 Mmult./s while operating at 1.5 V
Keywords :
CMOS logic circuits; adders; distributed arithmetic; integrated circuit design; logic design; multiplying circuits; 0.35 micron; 1.5 V; 15 mW; Mietec standard CMOS technology; complex multiplier; distributed arithmetic; overturned-stairs adder tree; regular layout; Adders; Arithmetic; Broadband communication; CMOS technology; Communication cables; Energy consumption; Modems; OFDM; Routing; Table lookup;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812214
