A fast scheme and implementation for n-bit squarer

The square of an n-bit unsigned number is a special case of multiplication when the two inputs are equal. This means that, the partial-product (PP) matrix is symmetrical across the main diagonal. Using this symmetry property, it is possible to reduce the PP matrix to one with a smaller number of rows. This results in a significant saving of hardware and time delay. In this paper, a scheme is developed for a high-speed squarer which reduces the depth of the PP matrix from n to at most [(n-2)/4]+1 using at most three-level logic gates. Thus, the time required to perform the squaring of n-bit number is reduced by a factor of almost log (n/4)/log (n)