Automatic architecture evaluation for hardware/software codesign

Hardware/software codesign requires an accurate way of evaluating candidate architectures. Architecture exploration (which can be used to automate hardware/software codesign) requires an automatic way of evaluating candidate architectures, otherwise a substantial programming effort must be expended on each iteration. We present a system that automatically generates an instruction level simulator (ILS) and a hardware implementation model given a description of a candidate architecture. Accurate cycle counts can be obtained for specific applications using the ILS. At the same time, the hardware implementation model can be used to obtain cycle length, die size, and power consumption estimates. These measurements allow an accurate performance evaluation to be constructed for each candidate architecture. We use the machine description language ISDL to support the generation of the ILS and the hardware model, as well as other tools which form the core of our hardware/software codesign system